A survey of low power design techniques for last level caches

Ofori-Attah, E., Opoku Agyeman, M. and Wang, X. (2018) A survey of low power design techniques for last level caches. Poster presented to: 14th International Symposium on Applied Reconfigurable Computing (ARC 2018), Santorini, Greece, 2018-05-02.

Ofori_Attah_etal_2018_A_survey_of_low_power_design_techniques_for_last_level_caches (520kB)

Item Type:	Conference or Workshop Item (Poster)
Abstract:	The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming element. Consequently, there have been several efforts towards reducing power consumption in LLCs. This posters presents a survey of recent contribution towards reducing power consumption in the LLC.
Creators:	Ofori-Attah, Emmanuel, Opoku Agyeman, Michael and Wang, Xiaohang
Faculties, Divisions and Institutes:	Faculties > Faculty of Arts, Science & Technology > Computing
Date:	2 May 2018
Date Type:	Publication
Journal or Publication Title:	14th International Symposium on Applied Reconfigurable Computing (ARC 2018)
Event Title:	14th International Symposium on Applied Reconfigurable Computing (ARC 2018)
Event Dates:	2018-05-02
Event Location:	Santorini, Greece
Event Type:	Other
Language:	English
Status:	Published / Disseminated
Refereed:	Yes
Related URLs:	https://pure.northampton.ac.uk/en/public...
URI:	http://nectar.northampton.ac.uk/id/eprint/11678

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