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Architectural techniques for improving the power consumption of NoC-based CMPs: a case study of cache and network layer

Ofori-Attah, E., Bhebhe, W. and Opoku Agyeman, M. (2017) Architectural techniques for improving the power consumption of NoC-based CMPs: a case study of cache and network layer. Journal of Low Power Electronics and Applications. 7(2) 2079-9268.

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Abstract:
The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology. Miniaturized transistors invoke many-core integration at the cost of high power consumption caused by the components in NoC-based CMPs; particularly caches and routers. If NoC-based CMPs are to be standardised as the future of technology design, it is imperative that the power demands of its components are optimized. A lot of research effort has been put into finding techniques that can improve the power efficiency for both cache and router architectures. This work presents a survey of power saving techniques for efficient NoC designs with focus on the cache and router components such as the buffer and crossbar. Nonetheless, the aim of this work is to compile a quick reference guide of power saving techniques for engineers and researchers.
Creators:
Ofori-Attah, E., Bhebhe, W. and Opoku Agyeman, M.
Faculties, Divisions and Institutes:
Faculties > Faculty of Arts, Science & Technology > Computing
Date:
29 May 2017
Date Type:
Publication
Journal or Publication Title:
Journal of Low Power Electronics and Applications
Volume:
7
Number:
2
Language:
English
DOI:
10.3390/jlpea7020014
ISSN:
2079-9268
Status:
Published / Disseminated
Refereed:
Yes
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