A survey of low power design techniques for last level caches

Ofori-Attah, E. and Opoku Agyeman, M. (2018) A survey of low power design techniques for last level caches. Poster presented to: 14th International Symposium on Applied Reconfigurable Computing (ARC 2018), Santorini, Greece, 02-04 May 2018.

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Abstract:

The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming element. Consequently, there have been several efforts towards reducing power consumption in LLCs. This posters presents a survey of recent contribution towards reducing power consumption in the LLC.

Subjects:

T Technology > TK Electrical engineering. Electronics. Nuclear engineering > TK7800 Electronics > TK7885 Computer engineering. Computer hardware

Creators:

Ofori-Attah, E. and Opoku Agyeman, M.

Faculties, Divisions and Institutes:

Faculties > Faculty of Arts, Science & Technology > Computing

Date:

2 May 2018

Date Type:

Publication

Event Title:

14th International Symposium on Applied Reconfigurable Computing (ARC 2018)

Event Dates:

02-04 May 2018

Event Location:

Santorini, Greece

Event Type:

Conference

Language:

English

Status:

Published / Disseminated

Refereed:

Yes