Ofori-Attah, E. and Opoku Agyeman, M. (2016) A survey of low power techniques for efficient Network-on-Chip design. In: 23rd IEEE Symposium on High Performance Computer Architecture (HPCA). USA: IEEE. (Accepted)
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![[thumbnail of Paper.pdf]](https://nectar.northampton.ac.uk/style/images/fileicons/text.png "Paper.pdf")
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Abstract:
Power consumption continues to be a challenge for designers as the complexity of NoC increases. The scaling down of technology towards the deep nanometer era will only cause an increase in the amount of power NoC components will consume. Therefore, low power design solution is one of the essential requirements of future NoC-based System-on-Chip (SoC) applications. Several techniques have been proposed over the years to improve the performance of the NoCs, trading-off power efficiency; particularly power hungry elements in NoC routers. Power dissipation can be reduced by optimizing the router elements, applying architecture saving techniques and communication links. This paper presents recent contributions and efficient saving techniques at the router, NoC architecture and Communication link level.
Additional Information:
This paper to be presented at the First Workshop on Pioneering Processor Paradigms on 04 February 2017. The workshop is held in conjunction with the 23rd IEEE Symposium on High Performance Computer Architecture (HPCA) taking place from 04-08 February 2017 in Austin, Texas.
Subjects:
Creators:
Ofori-Attah, E. and Opoku Agyeman, M.
Publisher:
IEEE
Faculties, Divisions and Institutes:
Date:
19 December 2016
Date Type:
Acceptance
Title of Book:
23rd IEEE Symposium on High Performance Computer Architecture (HPCA)
Event Title:
First Workshop on Pioneering Processor Paradigms
Event Dates:
04 February 2017
Place of Publication:
USA
Event Location:
Austin, Texas
Event Type:
Workshop
Language:
English
Status:
Accepted
Refereed:
Yes
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