Ofori-Attah, E. and Opoku Agyeman, M. (2016) A survey of low power NoC design techniques. In: International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC). Sweden: ACM. (Accepted)
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Abstract:
As we usher into the billion-transistor era, NoC which was once deemed as the solution is defecting due to high power consumption in its components. Several techniques have been proposed over the years to improve the performance of the NoCs, trading off power efficiency. However, low power design solution is one of the essential requirements of future NoC-based SoC applications. Power dissipation can be reduced by efficient routers, architecture saving techniques and communication links. This paper presents recent contributions and efficient saving techniques at the router, NoC architecture and Communication link level.
Additional Information:
Paper to be presented at the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS) held 25 January 2017. The Workshop is part of the 12th HiPEAC (High-Performance Embedded Architectures and Compilers) Conference held 23-25 January 2017 in Stockholm, Sewden.
Uncontrolled Keywords:
Low Power NoC, Network-On-Chip, 3D NoC
Subjects:
Creators:
Ofori-Attah, E. and Opoku Agyeman, M.
Publisher:
ACM
Faculties, Divisions and Institutes:
Date:
9 December 2016
Date Type:
Acceptance
Title of Book:
International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC)
Event Title:
2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS)
Event Dates:
25 January 2017
Place of Publication:
Sweden
Event Location:
Stockholm, Sweden
Event Type:
Workshop
Language:
English
ISBN:
9781450321389
DOI:
Status:
Accepted
Refereed:
Yes
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