Northampton Electronic Collection of Theses and Research

A survey of recent contributions of high performance NoC architectures

Ofori-Attah, E. and Opoku Agyeman, M. (2016) A survey of recent contributions of high performance NoC architectures. In: IEEE Technically Sponsored Computing Conference 2017 :. London: IEEE. (In Press)

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OforiAttah20168985.pdf - Accepted Version
Information
Abstract:
The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by adjustments to the routers, the architecture itself and the communication links. In this paper, a survey is conducted on recent contributions and techniques employed by researchers towards the reduction of power in the router architecture, network architecture and communication links.
Uncontrolled Keywords:
Network-on-chip, communication links NoC, formatting, low power routerarchitecture, virtual channel sharing
Creators:
Ofori-Attah, E. and Opoku Agyeman, M.
Publisher:
IEEE
Faculties, Divisions and Institutes:
Faculties > Faculty of Arts, Science & Technology > Computing
Date:
14 November 2016
Date Type:
Acceptance
Title of Book:
IEEE Technically Sponsored Computing Conference 2017 :
Place of Publication:
London
Language:
English
Status:
In Press
Refereed:
Yes
Related URLs:
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