Zong, W., Wang, L., Xu, Q. and Opoku Agyeman, M. (2016) SlideAcross: a low-latency adaptive router for chip multi-processor. In: Kitsos, P. (ed.) Euromicro Conference on Digital System Design (DSD) (2016). U.S.: IEEE. 9781509028160. pp. 115-122.
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Abstract:
The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. This router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low loads. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a nonspeculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications’ execution time by 16.9% in average compared to low-latency router SWIFT
Subjects:
Creators:
Zong, W., Wang, L., Xu, Q. and Opoku Agyeman, M.
Editors:
Kitsos, P.
Publisher:
IEEE
Faculties, Divisions and Institutes:
Date:
30 September 2016
Date Type:
Publication
Page Range:
pp. 115-122
Title of Book:
Euromicro Conference on Digital System Design (DSD) (2016)
Event Title:
19th Euromicro Conference on Digital System Design (DSD) 2016
Event Dates:
31 August - 02 September 2016
Place of Publication:
U.S.
Event Location:
Limassol, Cyprus
Event Type:
Conference
Language:
English
ISBN:
9781509028160
DOI:
Status:
Published / Disseminated
Refereed:
Yes
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