Northampton Electronic Collection of Theses and Research

A survey of power-aware Network-on-Chip design techniques

Ofori-Attah, E. and Opoku Agyeman, M. (2018) A survey of power-aware Network-on-Chip design techniques. The Thirteenth International Multi-Conference on Computing in Global Information Technology. 2308-4529. (Accepted)

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Abstract:
The Network-on-Chip (NoC) paradigm has been heralded as the solution to the communication limitation that System-on-Chip (SoC) poses. As we usher into the billion-transistor era, NoC which was once deemed as the solution is defecting due to its power demanding components. Several techniques have been proposed over the years to improve the performance of the NoCs, trading off power efficiency. However, low power design solution is one of the essential requirements of future NoC- based SoC applications. Power dissipation can be reduced by efficient routers, architecture saving techniques and communication links. This paper presents recent contributions and efficient saving techniques at the router, NoC architecture and Communication link level.
Additional Information:
Paper presented at the Thirteenth International Multi-Conference on Computing in Global Information Technology (ICCGI 2018) held 24-28 June 2018 in Venice, Italy.
Subjects:
Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Creators:
Ofori-Attah, E. and Opoku Agyeman, M.
Publisher:
IARIA
Faculties, Divisions and Institutes:
Faculties > Faculty of Arts, Science & Technology > Computing
Date:
30 April 2018
Date Type:
Acceptance
Journal or Publication Title:
The Thirteenth International Multi-Conference on Computing in Global Information Technology
Event Type:
Conference
Language:
English
ISSN:
2308-4529
Status:
Accepted
Refereed:
Yes
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