Northampton Electronic Collection of Theses and Research

A study of techniques to increase Instruction Level Parallelism

Margarita Espinosa Jimenez, L. and Opoku Agyeman, M. (2018) A study of techniques to increase Instruction Level Parallelism. In: International Symposium on Computer Science and Intelligent Control. Sweden: ISCSIC. (Accepted)

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A Study of Techniques to Increase Instruction Level Parallelism.pdf - Submitted Version
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Abstract:
Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and according to the advances that have been obtained in hardware, this survey presents the different techniques that have been used successfully in the execution of multiple instructions of a single program in a single clock cycle.
Additional Information:
Paper presented at the 2nd International Symposium on Computer Science and Intelligent Control (ISCSIC 2018) held in Stockholm, Sweden, 21-23 September 2018.
Uncontrolled Keywords:
Instruction Level Parallelism, high performance, VLIW, pipelining
Subjects:
Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Creators:
Margarita Espinosa Jimenez, L. and Opoku Agyeman, M.
Publisher:
ISCSIC
Faculties, Divisions and Institutes:
Faculties > Faculty of Arts, Science & Technology > Computing
Date:
20 April 2018
Date Type:
Acceptance
Title of Book:
International Symposium on Computer Science and Intelligent Control
Place of Publication:
Sweden
Event Type:
Conference
Language:
English
Status:
Accepted
Refereed:
Yes
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