Northampton Electronic Collection of Theses and Research

A survey of low power design techniques for last level caches

Ofori-Attah, E., Wang, X. and Opoku Agyeman, M. (2018) A survey of low power design techniques for last level caches. Lecture Notes in Computer Science. 10824 0302-9743.

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Information
Abstract:
The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming elements. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.
Creators:
Ofori-Attah, E., Wang, X. and Opoku Agyeman, M.
Faculties, Divisions and Institutes:
Faculties > Faculty of Arts, Science & Technology > Computing
Date:
8 April 2018
Date Type:
Publication
Journal or Publication Title:
Lecture Notes in Computer Science
Volume:
10824
Language:
English
DOI:
10.1007/978-3-319-78890-6_18
ISSN:
0302-9743
Status:
Published / Disseminated
Refereed:
Yes
Related URLs:
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